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? semiconductor components industries, llc, 2016 september, 2016 ? rev. 0 1 publication order number: ncp1341/d ncp1341 high-voltage, quasi-resonant, controller featuring valley lock-out switching the ncp1341 is a highly integr ated quasi?resonant flyback controller suitable for designing high?performance off?line power converters. with an integrated active x2 capacitor discharge feature, the ncp1341 can enable no?load power consumption below 30 mw. the ncp1341 features a proprietary valley?lockout circuitry, ensuring stable valley switching. this system works down to the 6 th valley and transitions to frequency foldback mode to reduce switching losses. as the load decreases further, the ncp1341 enters quiet?skip mode to manage the power delivery while minimizing acoustic noise. the ncp1341 integrates power excursion mode (pem) to minimize transformer size in designs requiring high transient load capability. if transient load capability is not desired, the ncp1340 offers the same performance and features without pem. to help ensure converter ruggedness, the ncp1341 implements several key protective features such as internal brownout detection, a non?dissipative over power protection (opp) for constant maximum output power regardless of input voltage, a latched overvoltage and ntc?ready overtemperature protection through a dedicated pin, and line removal detection to safely discharge the x2 capacitors when the ac line is removed. features ? integrated high?voltage startup circuit with brownout detection ? integrated x2 capacitor discharge capability ? wide v cc range from 9 v to 28 v ? 28 v v cc overvoltage protection ? abnormal overcurrent fault protection for winding short circuit or saturation detection ? internal temperature shutdown ? valley switching operation with valley?lockout for noise?free operation ? frequency foldback with 25 khz minimum frequency clamp for increased efficiency at light loads ? skip mode with quiet?skip technology for highest performance during light loads ? minimized current consumption for no load power below 30 mw ? frequency jittering for reduced emi signature ? latching or auto?recovery timer?based overload protection ? adjustable overpower protection (opp) ? fixed or adjustable maximum frequency clamp ? fault pin for severe fault conditions, ntc compatible for otp (9?pin v ersion only) ? 4 ms soft?start timer pin connections (top views) soic?9 nb d suffix case 751bp www. onsemi.com see detailed ordering and shipping information on page 2 o f this data sheet. ordering information 1 9 1341xz = specific device code x = a or b z = 1, 2 or 3 a = assembly location l = wafer lot y = year w = work week = pb?free package marking diagram 1341xz alyw 1 9 gnd drv vcc hv fmax fb zcd/opp cs fault 1 fb zcd/opp cs fmax gnd drv vcc hv 1 soic?8 nb d suffix case 751 1 8
ncp1341 www. onsemi.com 2 typical application schematic figure 1. ncp1341 8?pin typical application circuit l n emi filter + + ++ zcd/opp fb cs gnd drv vcc hv vout ncp1341xx fmax figure 2. ncp1341 9?pin typical application circuit l n emi filter + + ++ zcd/opp fb cs gnd drv vcc hv vout ncp1341xx fault ?to fmax table 1. orderable part numbers ordering code device marking pins fault pin fmax pin pem fault/overload protection frequency clamp NCP1341B1DR2G 1341b1 8 no yes yes auto?restart none ncp1341b1d1r2g 1341b1 9 yes yes yes auto?restart none
ncp1341 www. onsemi.com 3 functional block diagram figure 3. ncp1341 block diagram fb cs r q s r fb t leb1 opp zcd/opp k fb i cs v dd clamp v cc drv gnd vcc x2/bo detect + v cc management hv x2 fmax control fault i fb v fb(open) on?time control ilim1 detect t leb2 ilim2 detect jitter ramp count 4 abnormal ocp opp control opp off?time control dead?time control valley/vco control fb qr_fmax t tout quiet?skip control fb fault management bo v cc(ovp) tsd ovld t ovld abnormal ocp ovld fault qr_fmax ovp/otp detect ovp otp ovp otp v fault(clamp) fault i otp v dd r fault(clamp) fmax i fmax v dd pem_fmax pem detect pem pem_fmax fb pem control pem pem 8?pin 9?pin table 2. pin functional description 8?pin 9?pin pin name function ? 1 fault the controller enters fault mode if the voltage on this pin is pulled above or below the fault thresholds. a precise pull up current source allows direct interface with an ntc thermistor. 1 2 fmax a resistor to ground sets the value for the maximum switching frequency in ccm mode. for ver- sions x3, it also sets the maximum switching frequency in qr mode. for versions a/b, pulling this pin above 4 v switches the pem control method to fixed frequency mode. 2 3 fb feedback input for the qr flyback controller. allows direct connection to an optocoupler. 3 4 zcd/opp a resistor divider from the auxiliary winding to this pin provides input to the demagnetization de- tection comparator and sets the opp compensation level. 4 5 cs input to the cycle?by?cycle current limit comparator. 5 6 gnd ground reference. 6 7 drv this is the drive pin of the circuit. the drv high?current capability (?0.5 /+0.8 a) makes it suit- able to effectively drive high gate charge power mosfets. 7 8 vcc this pin is the positive supply of the ic. the circuit starts to operate when v cc exceeds 17 v and turns off when v cc goes below 9 v (typical values). after start?up, the operating range is 9 v up to 28 v. ? 9 n/c removed for creepage distance. 8 10 hv this pin is the input for the high voltage startup and brownout detection circuits. it also contains the line removal detection circuit to safely discharge the x2 capacitors when the line is removed.
ncp1341 www. onsemi.com 4 table 3. maximum ratings rating symbol value unit high voltage startup circuit input voltage v hv(max) ?0.3 to 700 v high voltage startup circuit input current i hv(max) 20 ma supply input voltage v cc(max) ?0.3 to 30 v supply input current i cc(max) 30 ma supply input voltage slew rate dv cc /dt 1 v/ s fault input voltage v fault(max) ?0.3 to v cc + 0.7 v v fault input current i fault(max) 10 ma zero current detection and opp input voltage v zcd(max) ?0.3 to v cc + 0.7 v v zero current detection and opp input current i zcd(max) ?2/+5 ma maximum input voltage (other pins) v max ?0.3 to 5.5 v maximum input current (other pins) i max 10 ma driver maximum voltage (note 1) v drv ?0.3 to v drv(high) v driver maximum current i drv(src) i drv(snk) 500 800 ma operating junction temperature t j ?40 to 125 c storage temperature range t stg ?60 to 150 c power dissipation (t a = 25 c, 1 oz cu, 0.155 sq inch printed circuit copper clad) tbd suffix, plastic package tbd (soic?9) p d(max) 450 mw thermal resistance, junction to ambient 1 oz cu printed circuit copper clad) tbd suffix, plastic package tbd (soic?9) r ja 225 c/w esd capability (note 5) human body model per jedec standard jesd22?a114e. charge device model per jedec standard jesd22?c101e. 2000 1000 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. maximum driver voltage is limited by the driver clamp voltage, v drv(high) , when v cc exceeds the driver clamp voltage. otherwise, the maximum driver voltage is v cc . 2. maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum?rated conditions is not implied. functional operation should be restricted to the recommended operating conditions. 3. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78. 4. low conductivity board. as mounted on 80 x 100 x 1.5 mm fr4 substrate with a single layer of 50 mm 2 of 2 oz copper trances and heat spreading area. as specified for a jedec51?1 conductivity test pcb. test conditions were under natural convection of zero air flow. 5. hv pin is rated to the maximum voltage of the part, or 700 v.
ncp1341 www. onsemi.com 5 table 4. electrical characteristics: (v cc = 12 v, v hv = 120 v, v fault = open, v fb = 2 v, v cs = 0 v, v zcd = 0 v, v fmax = 0 v, c vcc = 100 nf , c drv = 100 pf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics conditions symbol min typ max unit start?up and supply circuits supply voltage startup threshold discharge voltage during line removal minimum operating voltage operating hysteresis internal latch / logic reset level transition from i start1 to i start2 dv/dt = 0.1 v/ms v cc increasing v cc decreasing v cc decreasing v cc(on) ? v cc(off) v cc decreasing v cc increasing, i hv = 650 a v cc(on) v cc(x2_reg) v cc(off) v cc(hys) v cc(reset) v cc(inhibit) 16.0 17.0 8.5 7.5 4.5 0.40 17.0 18.0 9.0 ? 6.5 0.70 18.0 19.0 9.5 ? 7.5 1.05 v v cc(off) delay v cc decreasing t delay(vcc_off) 25 32 40 s startup delay delay from v cc(on) to drv enable t delay(start) ? ? 500 s minimum voltage for start?up current source v hv(min) ? ? 40 v inhibit current sourced from v cc pin v cc = 0 v i start1 0.2 0.5 0.65 ma start?up current sourced from v cc pin v cc = v cc(on) ? 0.5 v i start2 2.4 3.75 5.0 ma start?up circuit off?state leakage cur- rent v hv = 162.5 v v hv = 325 v v hv = 700 v i hv(off1) i hv(off2) i hv(off3) ? ? ? ? ? ? 15 20 50 a supply current fault or latch skip mode (excluding fb current) operating current v cc = v cc(on) ? 0.5 v v fb = 0 v f sw = 50 khz, c drv = open i cc1 i cc2 i cc3 ? ? ? 0.115 0.230 1.0 0.150 0.315 1.5 ma v cc overvoltage protection threshold v cc(ovp) 27 28 29 v v cc overvoltage protection delay t delay(vcc_ovp) 25 32 40 s x2 capacitor discharge line voltage removal detection timer t line(removal) 65 100 135 ms discharge timer duration t line(discharge) 21 32 43 ms line detection timer duration t line(detect) 21 32 43 ms v cc discharge current v cc = 20 v i cc(discharge) 13 18 23 ma hv discharge level v hv(discharge) ? ? 30 v brownout detection system start?up threshold v hv increasing v bo(start) 107 112 116 v brownout threshold v hv decreasing v bo(stop) 93 98 102 v hysteresis v hv increasing v bo(hys) 9.0 14 ? v brownout detection blanking time v hv decreasing t bo(stop) 40 70 100 ms gate drive rise time v drv from 10% to 90% t drv(rise) ? 20 40 ns fall time v drv from 90% to 10% t drv(fall) ? 5 30 ns current capability source sink i drv(src) i drv(snk) ? ? 500 800 ? ? ma high state voltage v cc = v cc(off) + 0.2 v, r drv = 10 k v cc = 30 v, r drv = 10 k v drv(high1) v drv(high2) 8.0 10 ? 12 ? 14 v low stage voltage v fault = 0 v v drv(low) ? ? 0.25 v feedback open pin voltage v fb(open) 4.9 5.0 5.1 v v fb to internal current setpoint division ratio k fb ? 3 ? ? internal pull?up resistor v fb = 0.4 v r fb 350 400 420 k internal pull?up current i fb 92 100 108 a
ncp1341 www. onsemi.com 6 table 4. electrical characteristics: (v cc = 12 v, v hv = 120 v, v fault = open, v fb = 2 v, v cs = 0 v, v zcd = 0 v, v fmax = 0 v, c vcc = 100 nf , c drv = 100 pf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions feedback valley thresholds transition from 1 st to 2 nd valley transition from 2 nd to 3 rd valley transition from 3 rd to 4 th valley transition from 4 th to 5 th valley transition from 5 th to 6 th valley transition from 6 th to 5 th valley transition from 5 th to 4 th valley transition from 4 th to 3 rd valley transition from 3 rd to 2 nd valley transition from 2 nd to 1 st valley v fb decreasing v fb decreasing v fb decreasing v fb decreasing v fb decreasing v fb increasing v fb increasing v fb increasing v fb increasing v fb increasing v 1to2 v 2to3 v 3to4 v 4to5 v 5to6 v 6to5 v 5to4 v 4to3 v 3to2 v 2to1 0.987 0.846 0.776 0.705 0.635 1.199 1.269 1.340 1.410 1.551 1.050 0.900 0.825 0.750 0.675 1.275 1.350 1.425 1.500 1.650 1.113 0.954 0.874 0.795 0.715 1.352 1.431 1.511 1.590 1.749 v maximum frequency clamp versions a2/b2/c2/d2/e2/f2 versions a3/b3/c3/d3/e3/f3 versions a3/b3/c3/d3/e3/f3 v fmax = 0.7 v v fmax = 3.5 v f max1 f max2 f max3 100 300 60 110 360 75 120 420 85 khz fmax secondary mode threshold v fmax(mode) 3.85 4.00 4.15 v fmax pin source current i fmax 9.0 10 11 a maximum on time t on(max) 28 32 40 s demagnetization input zcd threshold voltage v zcd decreasing v zcd(trig) 35 60 90 mv zcd hysteresis v zcd increasing v zcd(hys) 15 25 55 mv demagnetization propagation delay v zcd step from 4.0 v to ?0.3 v t demag ? 80 250 ns zcd clamp voltage positive clamp negative clamp i qzcd = 5.0 ma i qzcd = ?2.0 ma v zcd(max) v zcd(min) 12.4 ?0.9 12.7 ?0.7 13 0 v blanking delay after turn?off t zcd(blank) 2.7 3.0 3.5 s timeout after last demagnetization detection while in soft?start after soft?start complete t (tout1) t (tout2) 80 5.1 100 6.0 120 6.9 s current sense current limit threshold voltage version c/d version a/b/e/f v cs increasing v ilim1 0.76 0.95 0.80 1.00 0.84 1.05 v leading edge blanking duration drv minimum width minus t delay(ilim1) t leb1 220 265 330 ns current limit threshold propagation delay step v cs 0 v to v ilim1 + 0.5 v, v fb = 4 v t delay(ilim1) ? 95 175 ns pwm comparator propagation delay step v cs 0 v to 0.7 v, v fb = 2 v t delay(pwm) ? 125 175 ns minimum peak current freeze setpoint v freeze 170 200 230 mv abnormal overcurrent fault threshold version c/d version a/b/e/f v cs increasing, v fb = 4 v v ilim2 1.125 1.400 1.200 1.500 1.275 1.600 v abnormal overcurrent fault blanking duration drv minimum width minus t delay(ilim2) t leb2 80 110 140 ns abnormal overcurrent fault propagation delay step v cs 0 v to v ilim2 + 0.5 v, v fb = 4 v t delay(ilim2) ? 80 175 ns number of consecutive abnormal overcur- rent faults to enter latch mode n ilim2 ? 4 ? overpower protection delay v cs dv/dt = 1 v/ s, measured from v opp(max) to drv falling edge t opp(delay) ? 95 175 ns overpower signal blanking delay t opp(blank) 220 280 330 ns pull?up current source v cs = 1.5 v i cs 0.7 1.0 1.5 a
ncp1341 www. onsemi.com 7 table 4. electrical characteristics: (v cc = 12 v, v hv = 120 v, v fault = open, v fb = 2 v, v cs = 0 v, v zcd = 0 v, v fmax = 0 v, c vcc = 100 nf , c drv = 100 pf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions jittering jitter frequency f jitter 1.0 1.3 1.6 khz peak jitter voltage added to pwm comparator v jitter 90 100 115 mv power excursion mode pem activation threshold versions a/b/c/d versions e/f v pem 0.760 0.630 0.800 0.667 0.840 0.705 v maximum duty ratio during pem d max ? 75 ? % maximum fb voltage for off?time scaling v fb increasing v fb(max) 3.5 ? ? v maximum frequency scaling during pem v fb = 3.6 v k scale(max) 2.2 ? ? ? pem arming threshold v pem(arm) 1.0 1.5 2.0 v fault protection soft?start period measured from 1 st drv pulse to v cs = v ilim1 t sstart 2.8 4.0 5.0 ms flyback overload fault timer v cs = v ilim1 t ovld 120 160 200 ms overvoltage protection (ovp) threshold v fault increasing v fault(ovp) 2.79 3.00 3.21 v ovp detection delay v fault increasing t delay(ovp) 22.5 30 37.5 s overtemperature protection (otp) threshold (note 6) v fault decreasing v fault(otp_in) 380 400 420 mv overtemperature protection (otp) exiting threshold (note 6) v fault increasing versions b/d/f only v fault(otp_out) 874 910 966 mv otp detection delay v fault decreasing t delay(otp) 22.5 30 37.5 s otp pull?up current source v fault = v fault(otp_in) + 0.2 v i otp 42.5 45.0 48.5 a fault input clamp voltage v fault(clamp) 1.15 1.7 2.25 v fault input clamp series resistor r fault(clamp) 1.32 1.55 1.78 k autorecovery timer t restart 1.8 2.0 2.2 s light/no load management minimum frequency clamp f min 21.5 25 27.0 khz dead?time added during frequency foldback v fb = 300 mv t dt(max) 34 ? ? s quiet?skip timer t quiet 1.25 ? ? ms skip threshold v fb decreasing v skip 263 300 337 mv skip hysteresis v fb increasing v skip(hys) 10.0 37.5 60.0 mv thermal protection thermal shutdown temperature increasing t shdn ? 140 ? c thermal shutdown hysteresis temperature decreasing t shdn(hys) ? 40 ? c 6. ntc with r110 = 8.8 k
ncp1341 www. onsemi.com 8 introduction the ncp1341 implements a quasi?resonant flyback converter utilizing current?mode architecture where the switch?off event is dictated by the peak current. this ic is an ideal candidate where low parts count and cost effectiveness are the key parameters, particularly in ac?dc adapters, open?frame power supplies, etc. the ncp1341 incorporates all the necessary components normally needed in modern power supply designs, bringing several enhancements such as non?dissipative overpower protection (opp), brownout protection, and frequency reduction management for optimized efficiency over the entire power range. accounting for the needs of extremely low standby power requirements, the controller features minimized current consumption and includes an automatic x2 capacitor discharge circuit that eliminates the need to install power?consuming resistors across the x2 input capacitors. a novel power excursion mode (pem) is also included to allow brief operation in ccm at up to 2x the maximum output power without the need for a larger transformer. ? high?v oltage start?up cir cuit: low standby power consumption cannot be obtained with the classic resistive start?up circuit. the ncp1341 incorporates a high?voltage current source to provide the necessary current during start?up and then turns off during normal operation. ? internal brownout protection: the ac input voltage is sensed via the high?voltage pin. when this voltage is too low, the ncp1341 stops switching. no restart attempt is made until the ac input voltage is back within its normal range. ? x2?capacitor discharge circuitry: per the iec60950 standard, the time constant of the x2 input capacitors and their associated discharge resistors must be less than 1 s in order to avoid electrical shock when the user unplugs the power supply and inadvertently touches the ac input cord terminals. by providing an automatic means to discharge the x2 capacitors, the ncp1341 eliminates the need to install x2 discharge resistors, thus reducing power consumption. ? quasi?resonant, current?mode operation: quasi?resonant (qr) mode is a highly efficient mode of operation where the mosfet turn?on is synchronized with the point where its drain?source voltage is at the minimum (valley). a drawback of this mode of operation is that the operating frequency is inversely proportional to the system load. the ncp1341 incorporates a valley lockout (vlo) and frequency foldback technique to eliminate this drawback, thus maximizing the efficiency over the entire power range. ? valley lockout: in order to limit the maximum frequency while remaining in qr mode, one would traditionally use a frequency clamp. unfortunately, this can cause the controller to jump back and forth between two different valleys, which is often undesirable. the ncp1341 patented vlo circuitry solves this issue by determining the operating valley based on the system load, and locking out other valleys unless a significant change in load occurs. ? frequency foldback: as the load continues to decrease, it becomes beneficial to reduce the switching frequency. when the load is light enough, the ncp1341 enters frequency foldback mode. during this mode, the peak current is frozen and dead?time is added to the switching cycle, thus reducing the frequency and switching operation to discontinuous conduction mode (dcm). dead?time continues to be added until skip mode is reached, or the switching frequency reaches its minimum level of 25 khz. ? skip mode: to further improve light or no?load power consumption while avoiding audible noise, the ncp1341 enters skip mode when the operating frequency reaches its minimum value. foldback isavoid acoustic noise, the circuit prevents the switching frequency from decaying below 25 khz. this allows regulation via burst of pulses at 25 khz or greater instead of operating in the audible range. ? quiet?skip: to further reduce acoustic noise, the ncp1341 incorporates a novel circuit to prevent the skip mode burst period from entering the audible range as well. ? internal opp: in order to limit power delivery at high line, a scaled version of the negative voltage present on the auxiliary winding during the on?time is routed to the zcd/opp pin. this provides the designer with a simple and non?dissipative means to reduce the maximum power capability as the bulk voltage increases. ? frequency jittering: in order to reduce the emi signature, a low frequency triangular voltage waveform is added to the iniput of the pwm comparator. this helps by spreading out the energy peaks during noise analysis. ? internal soft?start: the ncp1341 includes a 4 ms soft?start to prevent the main power switch from being overly stressed during start?up. soft?start is activated each time a new startup sequence occurs or during auto?recovery mode. ? dedicated fault input: the ncp1341 includes a dedicated fault input. it can be used to sense an overvoltage condition and latch off the controller by pulling the pin above the overvoltage protection (ovp) threshold. the controller is also disabled if the fault pin is pulled below the overtemperature protection (otp)
ncp1341 www. onsemi.com 9 threshold. the otp threshold is configured for use with a ntc thermistor. ? overload/short?circuit protection: the ncp1341 implements overload protection by limiting the maximum time duration for operation during overload conditions. the overload timer operates whenever the maximum peak current is reached. in addition to this, special circuitry is included to prevent operation in ccm during extreme overloads, such as an output short?circuit. ? maximum frequency clamp: the ncp1341 includes a maximum frequency clamp. in all versions, the clamp is available disabled or fixed at 110 khz. it can also be adjusted via an external resistor from the fmax pin to ground, or be disabled by pulling the fmax pin above 4 v. ? power excursion mode (pem): when the power demand exceeds the power excursion threshold, the ncp1341 enters power excursion mode (pem) and forces the system into ccm to allow momentary power excursions of up to 2x for a and b versions or 1.5x for c and d versions, thus reducing or eliminating the need for a larger transformer. for versions e and f, the pem control mode is set to fixed frequency, where the switching frequency is frozen and the peak current is increased to achieve 2x power. this allows for lower switching losses at the expense of a slightly larger transformer. this is also accomplished in versions a and b to achieve 1.5x power by pulling the fmax pin above 4 v. high voltage start?up the ncp1341 contains a multi?functional high voltage (hv) pin. while the primary purpose of this pin is to reduce standby power while maintaining a fast start?up time, it also incorporates brownout detection and line removal detection. the hv pin must be connected directly to the ac line in order for the x2 dischar ge circuit to function correctly. line and neutral should be diode ?ored? before connecting to the hv pin as shown in figure 4. the diodes prevent the pin voltage from going below ground. a resistor in series with the pin should be used to protect the pin during emc or surge testing. a low value resistor should be used (<5 k ) to reduce the voltage offset during start?up. figure 4. high?voltage input connection emi ac con hv controller start?up and v cc management during start?up, the current source turns on and charges the v cc capacitor with i start2 (typically 6 ma). when v cc reaches v cc(on) (typically 16.0 v), the current source turns off. if the input voltage is not high enough to ensure a proper start?up (i.e. v hv has not reached v bo(start) ), the controller will not start. v cc then begins to fall because the controller bias current is at i cc2 (typically 1 ma) and the auxiliary supply voltage is not present. when v cc falls to v cc(off) (typically 10.5 v), the current source turns back on and charges v cc . this cycle repeats indefinitely until v hv reaches v bo(start) . once this occurs, the current source immediately turns on and charges v cc to v cc(on) , at which point the controller starts (see figure 6). when v cc is brought below v cc(inhibit) , the start?up current is reduced to i start1 (typically 0.5 ma). this limits power dissipation on the device in the event that the v cc pin is shorted to ground. once v cc rises back above v cc(inhibit) , the start?up current returns to i start2 . once v cc reaches v cc(on) , the controller is enabled and the controller bias current increases to i cc3 (typically 2.0 ma). however, the total bias current is greater than this due to the gate charge of the external switching mosfet. the increase in i cc due to the mosfet is calculated using equation 1. i cc f sw q g 10 ?3 (eq. 1) where i cc is the increase in milliamps, f sw is the switching frequency in kilohertz and q g is the gate charge of the external mosfet in nanocoulombs. c vcc must be sized such that a v cc voltage greater than v cc(off) is maintained while the auxiliary supply voltage increases during start?up. if c vcc is too small, v cc will fall below v cc(off) and the controller will turn off before the auxiliary winding supplies the ic. the total i cc current after the controller is enabled (i cc3 plus i cc ) must be considered to correctly size c vcc .
ncp1341 www. onsemi.com 10 figure 5. start?up circuitry block diagram start?up current = i start1 start?up current = i start2 v bo(start) v hv v hv(min) v cc v cc(on) v cc(off) v cc(inhibit ) drv t delay (start ) figure 6. start?up timing
ncp1341 www. onsemi.com 11 driver the ncp1341 maximum supply voltage, v cc(max) , is 28 v. typical high?voltage mosfets have a maximum gate voltage rating of 20 v. the drv pin incorporates an active voltage clamp to limit the gate voltage on the external mosfets. the drv voltage clamp, v drv(high) is typically 12 v with a maximum limit of 14 v. regulation control peak current control the ncp1341 is a peak current?mode controller, thus the fb voltage sets the peak current flowing in the transformer and the mosfet. this is achieved by sensing the mosfet current across a resistor and applying the resulting voltage ramp to the non?inverting input of the pwm comparator through the cs pin. the current limit threshold is set by applying the fb voltage divided by k fb (typically 3) to the inverting input of the pwm comparator. when the current sense voltage ramp exceeds this threshold, the output driver is turned of f, however, the peak current is affected by several functions (see figure 7): the peak current level is clamped during the soft?start phase. the setpoint is actually limited by a clamp level ramping from 0 to 1.0 v within 4 ms. in addition to the pwm comparator, a dedicated comparator monitors the current sense voltage, and if it reaches the maximum value, v ilim (typically 1.00 v), the gate driver is turned off and the overload timer is enabled. this occurs even if the limit imposed by the feedback voltage is higher than v ilim1 . due to the parasitic capacitances of the mosfet, a large voltage spike often appears on the cs pin at turn?on. to prevent this spike from falsely triggering the current sense circuit, the current sense signal is blanked for a short period of time, t leb1 (typically 275 ns), by a leading edge blanking (leb) circuit. figure 7 shows the schematic of the current sense circuit. the peak current is also limitied to a minimum level, v freeze (0.2 v, typically). this results in higher efficiency at light loads by increasing the minimum energy delivered per switching cycle, while reducing the overall number of switching cycles during light load. figure 7. current sense logic
ncp1341 www. onsemi.com 12 zero current detection the ncp1341 is a quasi?resonant (qr) flyback controller. while the power switch turn?off is determined by the peak current set by the feedback loop, the switch turn?on is determined by the transformer demagnetization. the demagnetization is detected by monitoring the transformer auxiliary winding voltage. turning on the power switch once the transformer is demagnetized has the benefit of reduced switching losses. once the transformer is demagnetized, the drain voltage starts ringing at a frequency determined by the transformer magnetizing inductance and the drain lump capacitance, eventually settling at the input voltage. a qr flyback controller takes advantage of the drain voltage ringing and turns on the power switch at the drain voltage minimum or ?valley? to reduce switching losses and electromagnetic interference (emi). as shown by figure 13, a valley is detected once the zcd pin voltage falls below the demagnetization threshold, v zcd(trig) , typically 55 mv. the controller will either switch once the valley is detected or increment the valley counter, depending on the fb voltage. overpower protection the average bulk capacitor voltage of the qr flyback varies with the rms line voltage. thus, the maximum power capability at high line can be much higher than desired. an integrated overpower protection (opp) circuit provides a relatively constant output power limit across the input voltage on the bulk capacitor, v bulk . since it is a high?voltage rail, directly measuring v bulk will contribute losses in the sensing network that will greatly impact the standby power consumption. the ncp1341 opp circuit achieves this without the need for a high?voltage sensing network, and is essentially lossless. figure 8. opp circuit schematic
ncp1341 www. onsemi.com 13 aux bulk p n v n ? ? ? ? v aux (v) figure 9. auxiliary winding voltage ? ? ? . since the auxiliary winding voltage during the power switch on time is a reflection of the input voltage scaled by the primary to auxiliary winding turns ratio, n p:aux (see figure 9), opp is achieved by scaling down reflected voltage during the on?time and applying it to the zcd pin as a negative voltage, v opp . the voltage is scaled down by a resistor divider comprised of r oppu and r oppl . the maximum internal current setpoint (v cs(opp) ) is simply the sum of v opp and the peak current sense threshold, v ilim1 . figure 8 shows the schematic for the opp circuit. as opp is added, eventually v ilim1 will equal v pem . at this point, any additional opp will reduce both thresholds equally. the adjusted peak current limit is calculated using equation 2. for example, a v opp of ?150 mv results in a peak current limit of 650 mv in ncp1341. v cs(opp) v opp v ilim1 (eq. 2) to ensure optimal zero?crossing detection, a diode is needed to bypass r oppu during the off?time. equation 3 is used to calculate r oppu and r oppl . r zcd r oppu r oppl n p:aux v bulk v opp v opp (eq. 3) r oppu is selected once a value is chosen for r oppl . r oppl is selected large enough such that enough voltage is available for the zero?crossing detection during the off?time. it is recommended to have at least 8 v applied on the zcd pin for good detection. the maximum voltage is internally clamped to v cc . the of f?time voltage on the zcd pin is given by equation 4. v zcd r oppl r zcd r oppl v aux v f (eq. 4) where v aux is the voltage across the auxiliary winding and v f is the d opp forward voltage drop. the ratio between r zcd and r oppl is given by equation 5. it is obtained by combining equations 3 and 4. r zcd r oppl v aux v f v zcd v zcd (eq. 5) a design example is shown below: system parameters: v aux 18 v v f 0.6 v n p:aux 0.18 the ratio between r zcd and r oppl is calculated using equation 5 for a minimum v zcd of 8 v. r zcd r oppl 18 v 0.6 v 8v 8v 1.2 k r zcd is arbitrarily set to 1 k . r oppl is also set to 1 k because the ratio between the resistors is close to 1. the ncp1341 maximum overpower compensation or peak current setpoint reduction is 31.25% for a v opp of ?250 mv. we will use this value for the following example: substituting values in equation 3 and solving for r oppu we obtain: r oppu 271 r oppl r zcd r oppu 271 1k 1k 270 k r zcd r oppu r oppl 0.18 370 v (?0.25 v) ?0.25 v 271 for optimum performance over temperature, it is recommended to keep r oppl below 3 k .
ncp1341 www. onsemi.com 14 soft?start soft?start is achieved by ramping up an internal reference, v sstart , and comparing it to the current sense signal. v sstart ramps up from 0 v once the controller initially powers up. the peak current setpoint is then limited by the v sstart ramp resulting in a gradual increase of the switch current during start?up. the soft?start duration, t sstart , is typically 4 ms. during startup, demagnetization phases are long and difficult to detect since the auxiliary winding voltage is very small. in this condition, the 6 s steady?state timeout is generally shorter than the inductor demagnetization period. if it is used to restart a switching cycle, it can cause operation in ccm for several cycles until the voltage on the zcd pin is high enough to prevent the timer from running. therefore, a longer timeout period, t tout1 (typically 100 s), is used during soft?start to prevent ccm operation. frequency jittering in order to help meet stringent emi requirements, the ncp1341 features frequency jittering to average the energy peaks over the emi frequency range. as shown in figure 10, the function consists of summing a 0 to 100 mv, 1.3 khz triangular wave (v jitter ) with the cs signal immediately before the pwm comparator. this current acts to modulate the on?time and hence the operation frequency. figure 10. jitter implementation since the jittering function modulates the peak current level, the fb signal will attempt to compensate for this ef fect in order to limit the output voltage ripple. therefore, the bandwidth of the feedback loop must be well below the jitter frequency, or the jitter function will be filtered by the loop. due to the frozen peak current, the effect of the jittering circuit will not be seen during frequency foldback mode. maximum frequency clamp the ncp1341 includes a maximum frequency clamp. in all versions, the clamp is available disabled or fixed at 110 khz. it can also be adjusted via an external resistor from the fmax pin to ground, or disabled by pulling the fmax pin above 4 v. the maximum frequency can be programmed using equation 6, and is shown in figure 11. f sw(max) 261 khz * 1 v r fmax *10 a (eq. 6) figure 11. f sw(max) vs. r fmax 1000 900 800 700 600 500 400 300 200 100 0 0 50 100 150 200 250 400 300 350 r fmax (k ) f sw(max) (khz)
ncp1341 www. onsemi.com 15 light load management valley lockout operation the operating frequency of a traditional qr flyback controller is inversely proportional to the system load. in other words, a load reduction increases the operating frequency. a maximum frequency clamp can be useful to limit the operating frequency range. however , when used by itself, such an approach often causes instabilities since when this clamp is active, the controller tends to jump (or hesitate) between two valleys, thus generating audible noise. instead, the ncp1341 also incorporates a patented valley lockout (vlo) circuitry to eliminate valley jumping. once a valley is selected, the controller stays locked in this valley until the output power changes significantly. this technique extends the qr mode operation over a wider output power range while maintaining good efficiency and limiting the maximum operating frequency. the operating valley (1 st , 2 nd , 3 rd, 4 th , 5 th or 6 th ) is determined by the fb voltage. an internal counter increments each time a valley is detected by the zcd/opp pin. figure 12 shows a typical frequency characteristic obtainable at low line in a 65 w application. 0 20 40 60 0 210 4 x 410 4 x 610 4 x 810 4 x 110 5 x pout (w) fsw (hz) 1 st 2 nd 3 rd 4 th 5 th 6 th vco mode 1 st 2 nd 3 rd 4 th 5 th 6 th vco mode figure 12. valley lockout frequency vs. output power when an ?n? valley is asserted by the valley selection circuitry, the controller is locked in this valley until the fb voltage decreases to the lower threshold (?n+1? valley activates) or increases to the ?n valley threshold? + 600 mv (?n?1? valley activates). the regulation loop adjusts the peak current to deliver the necessary output power. each valley selection comparator features a 600 mv hysteresis that helps stabilize operation despite the fb voltage swing produced by the regulation loop. table 5. valley fb thresholds (typical values) fb falling fb rising 1 st to 2 nd valley 1.050 v 2 nd to 1 st valley 1.650 v 2 nd to 3 rd valley 0.900 v 3 rd to 2 nd valley 1.500 v 3 rd to 4 th valley 0.825 v 4 th to 3 rd valley 1.425 v 4 th to 5 th valley 0.750 v 5 th to 4 th valley 1.350 v 5 th to 6 th valley 0.675 v 6 th to 5 th valley 1.275 v valley timeout in case of extremely damped oscillations, the zcd comparator may not be able to detect the valleys. in this condition, drive pulses will stop while the controller waits for the next valley or zcd event. the ncp1341 ensures continued operation by incorporating a maximum timeout period after the last demagnetization detection. the timeout signal acts as a substitute for the zcd signal to the valley counter. figure 13 shows the valley timeout circuit schematic. the steady state timeout period, t tout2 , is set at 6 s (typical) to limit the frequency step. during startup, the voltage offset added by the opp diode, d opp , prevents the zcd comparator from accurately detecting the valleys. in this condition, the steady state
ncp1341 www. onsemi.com 16 timeout period will be shorter than the inductor demagnetization period causing ccm operation. ccm operation lasts for a few cycles until the voltage on the zcd pin is high enough to detect the valleys. a longer timeout period, t tout1 , (typically 100 s) is set during soft?start to limit ccm operation. in vlo operation, the number of timeout periods are counted instead of valleys when the drain?source voltage oscillations are too damped to be detected. for example, if the fb voltage sets vlo mode to turn on at the fifth valley, and the zcd ringing is damped such that the zcd circuit is only able to detect: ? valleys 1 to 4: the circuit generates a drv pulse 6 s (steady?state timeout delay) after the 4 th valley detection. ? valleys 1 to 3: the timeout delay must run twice, and the circuit generates a drv pulse 12 s after the 3 rd valley detection. figure 13. valley timeout circuitry frequency foldback as the output load decreases (fb voltage decreases), the valleys are incremented from 1 to 6. when the sixth valley is reached, if the fb voltage further decreases to 0.6 v, the peak current setpoint becomes internally frozen to v freeze (0.2 v typically), and the controller enters frequency foldback mode (ff). during this mode, the controller regulates the power delivery by modulating the switching frequency. in frequency foldback mode, the controller reduces the switching frequency by adding dead?time after the 6 th valley is detected. this dead?time increases as the fb voltage decreases. there is no discontinuity when the system transitions from vlo to ff and the frequency smoothly reduces as fb decreases. the dead?time circuit is designed to add 0 s dead?time when v fb = 0.6 v and linearly increases the total dead?time to t dt(3) (32 s minimum) as v fb falls down to 0.3 v. the minimum frequency clamp prevents the switching frequency from dropping below 25 khz to eliminate the risk of audible noise. figure 14 summarizes the vlo to ff operation with respect to the fb voltage.
ncp1341 www. onsemi.com 17 valley 1 v fb (v) fault ! operating mode valley 3 valley 4 valley 5 valley 6 ff valley 2 v fb decreases v fb increases figure 14. valley lockout thresholds 0.60 0.67 0.75 0.82 0.90 1.05 1.28 1.35 1.43 1.50 1.65 3.5
ncp1341 www. onsemi.com 18 minimum frequency clamp and skip mode as mentioned previously, the circuit prevents the switching frequency from dropping below f min (25 khz typical). when the switching cycle would be longer than 40 s, the circuit forces a new switching cycle. however, the f min clamp cannot generate a drv pulse until the demagnetization is completed. in other words, it will not cause operation in ccm. since the ncp1341 forces a minimum peak current and a minimum frequency, the power delivery cannot be continuously controlled down to zero. instead, the circuit starts skipping pulses when the fb voltage drops below the skip level, v skip , and recovers operation when v fb exceeds v skip + v skip(hys) . this skip?mode method provides an efficient method of control during light loads. quiet?skip to further avoid acoustic noise, the circuit prevents the burst frequency during skip mode from entering the audible range by limiting it to a maximum of 800 hz. this is achieved via a timer (t quiet ) that is activated during quiet?skip. the start of the next burst cycle is prevented until this timer has expired. as the output power decreases, the switching frequency decreases. once it hits 25 khz, the skip?in threshold is reached and burst mode is entered ? switching stops as soon as the current drive pulses ends ? it does not stop immediately. once switching stops, fb will rise. as soon as fb crosses the skip?exit threshold, drive pulses will resume, but the controller remains in burst mode. at this point, a 1250 s (min) timer, t quiet , is started together with a count?to?3 counter. the next time the fb voltage drops below the skip?in threshold, drive pulses stop at the end of the current pulse as long as 3 drive pulses have been counted (if not, they do not stop until the end of the 3 rd pulse). they are not allowed to start again until the timer expires, even if the skip?exit threshold is reached first. it is important to note that the timer will not force the next cycle to begin ? i.e. if the natural skip frequency is such that skip?exit is reached after the timer expires, the drive pulses will wait for the skip?exit threshold. this means that during no?load, there will be a minimum of 3 drive pulses, and the burst?cycle period will likely be much longer than 1250 s. this operation helps to improve efficiency at no?load conditions. in order to exit burst mode, the fb voltage must rise higher than 800 mv. if this occurs before t quiet expires, the drive pulses will resume immediately ? i.e. the controller won?t wait for the timer to expire. figure 15 provides an example of how quiet?skip works.
ncp1341 www. onsemi.com 19 figure 15. quiet?skip timing diagram power excursion mode (pem) when the power demand exceeds the maximum power limit, the ncp1341 linearly increases the switching frequency forcing the power stage into ccm. versions c and d accomplish this by linearly increasing the switching frequency up to 2.5x, thus eliminating the need for a larger transformer. versions a and b achieve 2x power by also
ncp1341 www. onsemi.com 20 increasing the peak current by 25%, requiring a significantly smaller transformer than a converter that remained in qr mode. versions e and f achieve 2x power by freezing the switching frequency and increasing the peak current by 50%. this allows for lower switching losses at the expense of a slightly lar ger transformer. this is also accomplished in versions a and b by pulling the fmax pin above 4 v, however the power increase is limited to 1.5x. in all versions, the maximum switching frequency (and power) is set by the fmax pin. the ncp1341 contains a register to store the of f?time during qr mode. during each switching period, the off?time is measured and the register is updated. as long as the pem comparator is not tripped, this operation will continue indefinitely. when the pem comparator is tripped (due to an increase in power demand), the ncp1341 will enter pem on the following cycle. during pem, the stored value in the off?time register becomes a maximum off?time clamp, and when that clamp is reached, the next drive cycle will commence. since the demagnetization time of a qr flyback is directly proportional to the load, as the load increases, the system will naturally enter ccm with a fixed of f?time. the switching frequency is then determined by the on?time (which increases with load) and the fixed off?time. this operation alone provides a 1.5x power increase. in order to achieve 2x power, the off?time clamp is decreased linearly as the fb voltages increases. this has the effect of increasing the switching frequency to boost the output power. the frequency con tinues to be scaled until the maximum switching frequency (set by fmax) or the maximum feedback voltage, v fb(max) (3.5 v typical), is reached. this operation continues as long as the controller remains in pem, and the pem comparator is tripped before each drive turn?off. once a drive turn?off occurs without first tripping the pem comparator, pem is exited immediately (in the same cycle) and the controller immediately defaults back to qr mode with the next switching cycle starting at the zcd transition. since ccm operation is maintained via of f?time modulation instead of fixed?frequency duty cycle modulation, the system is naturally immune to subharmonic oscillations and slope compensation is not required. in addition to operation in ccm, the ncp1341 contains a maximum cs setpoint, v ilim1 (typically 1.0 v), to allow a 25% increase in peak current. when this comparator triggers, the drive pulse is terminated. this corresponds to a fb voltage of 3 v (typical). the v ilim1 comparator shares the same leb as the v pem comparator. while fb voltages higher than 3 v will not cause any additional increase in peak current, the switching frequency continues to increase until the fb pin reaches v fb(max) . at this point, the switching frequency will be scaled by a maximum value of k fscale(max) , 2.5 typical, provided fmax has not been reached. figure 16 shows the block schematic for pem, while figure 17 shows the timing for a fixed frequency. figure 18 shows the timing with a frequency excursion. figure 16. pem block diagram
ncp1341 www. onsemi.com 21 figure 17. pem timing for fixed frequency figure 18. pem timing for scaled frequency
ncp1341 www. onsemi.com 22 fault management the ncp1341 contains three separate fault modes. depending on the type of fault, the device will either latch off, restart when the fault is removed, or resume operation after the auto?recovery timer expires. latching faults some faults will cause the ncp1341 to latch off. these include the abnormal ocp (aocp), v cc ovp, and the external latch input. when the ncp1341 detects a latching fault, the driver is immediately disabled. the operation during a latching fault is identical to that of a non?latching fault except the controller will not attempt to restart at the next v cc(on) , even if the fault is removed. in order to clear the latch and resume normal operation, v cc must first be allowed to drop below v cc(reset) or a line removal event must be detected. this operation is shown in figure 19. time fault time v cc time fdrv v cc (on) v cc (off) fault applied time i hv i start 2 i start (off) fault removed figure 19. operation during latching fault
ncp1341 www. onsemi.com 23 non?latching faults when the ncp1341 detects a non?latching fault (brownout or thermal shutdown), the drivers are disabled, and v cc falls towards v cc(off) due to the ic internal current consumption. once v cc reaches v cc(off) , the hv current source turns on and c vcc begins to charge towards v cc(on) . when v cc , reaches v cc(on) , the cycle repeats until the fault is removed. once the fault is removed, the ncp1341 is re?enabled when v cc reaches v cc(on) according to the initial power?on sequence, provided v hv is above v bo(start). this operation is shown in figure 20. when v hv is reaches v bo(start) , v cc immediately charges to v cc(on) . if v cc is already above v cc(on) when the fault is removed, the controller will start immediately as long as v hv is above v bo(start). time fault time v cc time fdrv v cc (on ) v cc (off ) waits for next v cc(on) before starting fault applied time i hv i start 2 i start (off) fault removed figure 20. operation during non?latching fault
ncp1341 www. onsemi.com 24 auto?recovery timer faults some faults faults cause the ncp1341 auto?recovery timer to run. if an auto?recovery fault is detected, the gate drive is disabled and the auto?recovery timer, t autorec (typically 1.2 s), starts. while the auto?recovery timer is running, the hv current source turns on and off to maintain v cc between v cc(off) and v cc(on) . once the auto?recovery timer expires, the controller will attempt to start normally at the next v cc(on) provided v hv is above v bo(start) . this operation is shown in figure 21. time fault time v cc time drv v cc(on) v cc(off) fault applied autorecovery timer 1.2 s controller stops fault removed t restart restarts at v cc (on ) ( new burst cycle if fault still present ) figure 21. operation during auto?recovery fault
ncp1341 www. onsemi.com 25 protection features brownout protection a timer is enabled once v hv drops below its disable threshold, v bo(stop) (typically 99 v). the controller is disabled if v hv doesn?t exceed v bo(stop) before the brownout timer, t bo (typically 54 ms), expires. the timer is set long enough to ignore a two cycle dropout. the timer starts counting once v hv drops below v bo(stop) . figure 22 shows the brownout detector waveforms during a brownout. when a brownout is detected, the controller stops switching and enters non?latching fault mode (see figure 20). the hv current source alternatively turns on and off to maintain v cc between v cc(on) and v cc(off) until the input voltage is back above v bo(start) . v cc (on) v cc (off ) drv v cc brownout timer v hv v bo (stop ) v bo (start ) time time time time t delay (start ) starts charging immediately brownout detected restarts at next v cc(on) fault cleared figure 22. operation during brownout line removal detection and x2 capacitor discharge safety agency standards require the input filter capacitors to be discharged once the ac line voltage is removed. a resistor network is the most common method to meet this requirement. unfortunately, the resistor network consumes power across all operating modes and it is a major contributor of input power losses during light?load and no?load conditions. the ncp1341 eliminates the need for external discharge resistors by integrating active input filter capacitor discharge circuitry. a novel approach is used to reconfigure the high voltage startup circuit to discharge the input filter capacitors upon removal of the ac line voltage. the line removal detection circuitry is always active to ensure safety compliance. the line removal is detected by digitally sampling the voltage present at the hv pin, and monitoring the slope. a timer, t line(removal ) (typically 100 ms), is used to detect when the slope of the input signal is negative or below the resolution level. the timer is reset any time a positive slope is detected. once the timer expires, a line removal condition
ncp1341 www. onsemi.com 26 is acknowledged initiating an x2 capacitor discharge cycle, and the controller is disabled. if v cc is above v cc(on) , it is first discharged to v cc(on) . a second timer, t line(discharge) (typically 32 ms), is used for the time limiting of the discharge phase to protect the device against overheating. once the discharge phase is complete, t line(discharge) is reused while the device checks to see if the line voltage is reapplied. during the discharge phase, if v cc drops to v cc(on) , it is quickly recharged to v cc(x2_reg) . the discharging process is cyclic and continues until the ac line is detected again or the voltage across the x2 capacitor is lower than v hv(discharge) (30 v maximum). this feature allows the device to discharge large x2 capacitors in the input line filter to a safe level. it is important to note that the hv pin cannot be connected to any dc voltage due to this feature, i.e. directly to the bulk capacitor. v bo(start ) v bo(stop) t line(detect ) v hv(discharge ) t line(removal ) t line(discharge ) t line(discharge ) v cc(x2_reg) v cc(on) t line(removal ) t line(discharge /detect ) 0 i cc(discharge ) i cc3 i start 2 i start 2 x2 discharge current v cc v hv timer drv i cc time time x2 discharge x2 capacitor discharge x2 capacitor discharge device is stopped x2 discharge no ac detection ac line unplug ac timer starts ac timer restarts ac timer expires figure 23. line removal timing
ncp1341 www. onsemi.com 27 v bo(start ) v bo(stop ) v hv(discharge ) v cc(x2_reg) v cc(on) t line (removal ) t line (discharge ) t line (removal ) t line(discharge /detect ) i start 2 0 i cc(discharge ) i cc3 i start 2 time time time time time v hv drv v cc x2 discharge current timer i cc t delay (start ) x2 capacitor discharge ac line unplug device is stopped x2 discharge ac timer starts ac timer restarts ac timer expires ac detected figure 24. line removal timing with ac reapplied an over temperature protection block monitors the junction temperature during the discharge process to avoid thermal runaway, in particular during open/short pins safety tests. please note that the x2 discharge capability is also active at all times, including of f?mode and before the controller actually starts to pulse (e.g. if the user unplugs the converter during the start?up sequence). dedicated fault input the ncp1341 includes a dedicated fault input accessible via the fault pin (8?pin and 9?pin versions only). the controller can be latched by pulling up the pin above the upper fault threshold, v fault(ovp) (typically 3.0 v). the controller is disabled if the fault pin voltage is pulled below the lower fault threshold, v fault(otp_in) (typically 0.4 v). the lower threshold is normally used for detecting an overtemperature fault. the controller operates normally while the fault pin voltage is maintained within the upper and lower fault thresholds. figure 25 shows the architecture of the fault input. the fault input signal is filtered to prevent noise from triggering the fault detectors. upper and lower fault detector blanking delays, t delay(ovp) and t delay(otp) ,are both typically 30 s. a fault is detected if the fault condition is asserted for a period longer than the blanking delay.
ncp1341 www. onsemi.com 28 ovp an active clamp prevents the fault pin voltage from reaching the upper latch threshold if the pin is open. to reach the upper threshold, the external pull?up current has to be higher than the pull?down capability of the clamp (set by r fault(clamp) at v fault(clamp) ), i.e., approximately 1 ma. the upper fault threshold is intended to be used for an overvoltage fault using a zener diode and a resistor in series from the auxiliary winding voltage. the controller is latched once v fault exceeds v fault(ovp) . once the controller is latched, it follows the behavior of a latching fault according to figure 19 and is only reset if v cc is reduced to v cc(reset) , or x2 discharge is activated. in the typical application these conditions occur only if the ac voltage is removed from the system. otp the lower fault threshold is intended to be used to detect an overtemperature fault using an ntc thermistor. a pull up current source, i fault(otp) (typically 45.5 a), generates a voltage drop across the thermistor. the resistance of the ntc thermistor decreases at higher temperatures resulting in a lower voltage across the thermistor. the controller detects a fault once the thermistor voltage drops below v fault(otp_in) . the controller bias current is reduced during power up by disabling most of the circuit blocks including i fault(otp) . this current source is enabled once v cc reaches v cc(on) . a filter ca pacitor is typically connected between the fault and gnd pins. this will result in a delay before v fault reaches its steady state value once i fault(otp) is enabled. therefore, the lower fault comparator (i.e. overtemperature detection) is ignored during soft?start. version a latches off the controller after an overtemperature fault is detected according to figure 19. in version b, the controller is re?enabled once the fault is removed such that v fault increases above v fault(otp_out) , the auto?recovery timer expires, and v cc reaches v cc(on) as shown in figure 21. figure 25. fault pin internal schematic
ncp1341 www. onsemi.com 29 overload protection the overload timer integrates the duration of the overload fault. that is, the timer count increases while the fault is present and reduces its count once it is removed. the overload timer duration, t ovld , is typically 160 ms. when the overload timer expires, the controller detects an overload condition does one of the following: ? the controller latches off (versions a/c/e) or ? enters a safe, low duty?ratio auto?recovery mode (versions b/d/f). figure 26 shows the overload circuit schematic, while figure 27 and figure 28 show operating waveforms for latched and auto?recovery overload conditions. figure 26. overload circuitry count 4
ncp1341 www. onsemi.com 30 time fault time v cc time drv v cc(on) v cc(off) latch event latch time i hv i start2 i hv(off) figure 27. latched overload operation
ncp1341 www. onsemi.com 31 time fault flag time v cc time drv v cc(on) v cc(off) overcurrent applied time output load max load time fault timer 160 ms fault timer starts controller stops fault disappears t ovld t restart restarts at v cc ( on ) ( new burst cycle if fault still present ) t delay ( start ) figure 28. auto?recovery overload operation
ncp1341 www. onsemi.com 32 abnormal overcurrent protection (aocp) under some severe fault conditions, like a winding short?circuit, the switch current can increase very rapidly during the on?time. the current sense signal significantly exceeds v ilim1 , but because the current sense signal is blanked by the leb circuit during the switch turn?on, the power switch current can become huge and cause severe system damage. the ncp1341 protects against this fault by adding an additional comparator for abnormal overcurrent fault detection. the current sense signal is blanked with a shorter leb duration, t leb2 , typically 125 ns, before applying it to the abnormal overcurrent fault comparator. the voltage threshold of the comparator, v ilim2 , typically 1.5 v, is set 50% higher than v ilim1 , to avoid interference with normal operation. four consecutive abnormal overcurrent faults cause the controller to enter latch mode. the count to 4 provides noise immunity during surge testing. the counter is reset each time a drv pulse occurs without activating the fault overcurrent comparator. current sense pin failure protection a 1 a (typically) pull?up current source, i cs , pulls up the cs pin to disable the controller if the pin is left open. additionally, the maximum on?time, t on(max) (32 s typically), prevents the mosfet from staying on permanently if the cs pin is shorted to gnd. output short circuit protection during an output short?circuit, there is not enough voltage across the secondary winding to demagnetize the core. due to the valley timeout feature of the controller, the flux level will quickly walk up until the core saturates. this can cause excessive stress on the primary mosfet and secondary diode. this is not a problem for the ncp1341, however, because the valley timeout timer is disabled while the zcd pin voltage is above the arming threshold. since the leakage energy is high enough to arm the zcd trigger, the timeout timer is disabled and the next drive pulse is delayed until demagnetization occurs. in pem, the next drive pulse is not triggered by demagnetization, but must also be delayed if there is a short?circuit on the output. to accomplish this, the pem arming comparator, v pem(arm) (1.5 v typical), monitors the zcd pin voltage when in pem. at the turn?off of each drive cycle, the zcd voltage swings high and triggers this comparator. once the ccm timer expires, the next drive cycle will only start if the comparator has been triggered. during an output short?circuit, the aux winding voltage collapses, and the zcd pin will not swing high enough to trip the comparator. therefore, when the ccm timer expires the drive cycle will be delayed until demagnetization occurs, i.e. the controller will operate as if in qr mode. the short circuit protection block is shown in figure 29. figure 29. short circuit protection v cc overvoltage protection an additional comparator on the v cc pin monitors the v cc voltage. if vcc exceeds vcc(ovp), the gate drive is disabled and the ncp1341 follows the operation of a latching fault (see figure 19). thermal shutdown an internal thermal shutdown circuit monitors the junction temperature of the controller. the controller is disabled if the junction temperature exceeds the thermal shutdown threshold, t shdn (typically 140 c). when a thermal shutdown fault is detected, the controller enters a non?latching fault mode as depicted in figure 20. the controller restarts at the next v cc(on) once the junction temperature drops below below t shdn by the thermal shutdown hysteresis, t shdn(hys) , typically 40 c. the thermal shutdown is also cleared if v cc drops below v cc(reset) , or a line removal fault is detected. a new power up sequence commences at the next v cc(on) once all the faults are removed.
ncp1341 www. onsemi.com 33 typical characteristics 17.14 17.12 17.1 17.08 17.06 17.04 17.02 17 16.98 16.96 16.94 ?40 120 100 80 ?20 0 20 60 40 v cc(on) (v) t j , junction temperature ( c) figure 30. v cc(on) vs. temperature ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 31. v cc(off) vs. temperature 9 v cc(off) (v) 8.99 8.98 8.97 8.96 8.95 8.94 8.93 ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 32. i start1 vs. temperature 0.6 i start1 (ma) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 33. i start2 vs. temperature 5 i start2 (ma) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 34. i hv(off1) vs. temperature 7 i hv(off1) ( a) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 35. i hv(off2) vs. temperature 9 i hv(off2) ( a) 8 7 6 5 4 3 2 1 0 0.5 0.4 0.3 0.2 0.1 0 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 6 5 4 3 2 1 0
ncp1341 www. onsemi.com 34 typical characteristics 0.126 ?40 120 100 80 ?20 0 20 60 40 i cc1 (ma) t j , junction temperature ( c) figure 36. i cc1 vs. temperature ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 37. i cc2 vs. temperature 0.255 i cc2 (ma) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 38. i cc3 vs. temperature 1.075 i cc3 (ma) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 39. v cc(ovp) vs. temperature 28.35 v cc(ovp) (v) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 40. i cc(discharge) vs. temperature 19.8 i cc(discharge) (ma) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 41. v bo(start) vs. temperature 112.6 v bo(start) (v) 0.124 0.122 0.120 0.118 0.116 0.114 0.112 0.110 0.108 0.106 0.250 0.245 0.240 0.235 0.230 0.225 0.220 1.070 1.065 1.060 1.055 1.050 1.045 1.040 1.035 1.030 28.3 28.25 28.2 28.15 28.1 19.6 19.4 19.2 19 18.8 18.6 18.4 18.2 18 17.8 17.6 112.4 112.2 112 111.8 111.6 111.4 111.2 110 110.8
ncp1341 www. onsemi.com 35 typical characteristics 98.2 ?40 120 100 80 ?20 0 20 60 40 v bo(stop) (v) t j , junction temperature ( c) figure 42. v bo(stop) vs. temperature ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 43. t drv(rise) vs. temperature 90 t drv(rise) (ns) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 44. t drv(fall) vs. temperature 45 t drv(fall) (ns) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 45. f max1 vs. temperature 111.8 f max1 (khz) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 46. f max2 vs. temperature 367 f max2 (khz) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 47. f max3 vs. temperature 73.45 f max3 (khz) 98 97.8 97.6 97.4 97.2 97 111.6 111.4 111.2 111 110.8 110.6 110.4 110.2 366.5 366 365.5 365 364.5 364 363.5 363 362.5 73.4 73.35 73.3 73.25 73.2 73.15 73.1 73.05 73 80 70 60 50 40 30 20 10 0 cdrv = 100 pf cdrv = 1 nf cdrv = 100 pf cdrv = 1 nf 40 35 30 25 20 15 10 5 0
ncp1341 www. onsemi.com 36 typical characteristics 32.5 ?40 120 100 80 ?20 0 20 60 40 t on(max) ( s) t j , junction temperature ( c) figure 48. t on(max) vs. temperature ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 49. v zcd(trig) vs. temperature 63.6 v zcd(trig) (mv) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 50. v zcd(hys) vs. temperature 25.65 v zcd(hys) (mv) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 51. v zcd(max) vs. temperature 12.95 v zcd(max) (v) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 52. v zcd(min) vs. temperature 0 v zcd(min) (v) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 53. v freeze vs. temperature 198.8 v freeze (mv) 32.4 32.3 32.2 32.1 32 31.9 31.8 31.7 63.5 63.4 63.3 63.2 63.1 63 25.6 25.55 25.5 25.45 25.4 25.35 12.9 12.85 12.8 12.75 12.7 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?0.7 ?0.8 ?0.9 198.6 198.4 198.2 198 197.8 197.6
ncp1341 www. onsemi.com 37 typical characteristics 1.31 ?40 120 100 80 ?20 0 20 60 40 f jitter (khz) t j , junction temperature ( c) figure 54. f jitter vs. temperature ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 55. v jitter vs. temperature 104.2 v jitter (mv) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 56. v fault(ovp) vs. temperature 3.1 v fault(ovp) (v) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 57. v fault(otp_in) vs. temperature 402.5 v fault(otp_in) (mv) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 58. v fault(otp_out) vs. temperature 920 v fault(otp_out) (mv) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 59. i otp vs. temperature 45.1 i otp ( a) 1.308 1.306 1.304 1.302 1.3 1.298 1.296 1.294 3.09 3.08 3.07 3.06 3.05 3.04 3.03 45 44.9 44.8 44.7 44.6 44.5 44.4 44.3 402 401.5 401 400.5 400 399.5 399 918 916 914 912 910 908 906 104 103.8 103.6 103.4 103.2 103 102.8
ncp1341 www. onsemi.com 38 typical characteristics 1.731 ?40 120 100 80 ?20 0 20 60 40 v fault(clamp) (v) t j , junction temperature ( c) figure 60. v fault(clamp) vs. temperature ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 61. r fault(clamp) vs. temperature 1.55 r fault(clamp) (k ) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 62. f min vs. temperature 24.5 f min (khz) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 63. t quiet vs. temperature 1.39 t quiet (ms) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 64. t zcd(blank) vs. temperature 3.2 t zcd(blank) ( s) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 65. v ilim1 vs. temperature 1.001 v ilim1 (v) 1.73 1.729 1.728 1.727 1.726 1.545 1.54 1.535 1.53 1.525 1.52 1.515 1.51 1.505 1.5 1.495 24.45 24.4 24.35 24.3 24.25 24.2 24.15 24.1 24.05 24 1.385 1.38 1.375 1.37 1.365 3.18 3.16 3.14 3.12 3.1 3.08 3.06 3.04 1 0.999 0.998 0.997 0.996 0.995 0.994 0.993 0.992
ncp1341 www. onsemi.com 39 typical characteristics 1.503 ?40 120 100 80 ?20 0 20 60 40 v ilim2 (v) t j , junction temperature ( c) figure 66. v ilim2 vs. temperature ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) 40.2 t dt(max) ( s) ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) figure 67. t dt(max) vs. temperature 297 v skip (mv) figure 68. v skip vs. temperature 1.502 1.501 1.5 1.499 1.498 1.497 1.496 1.495 1.494 1.493 1.492 296.5 296 295.5 295 294.5 294 ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) 0.802 v pem (versions a/b/c/d) (v) figure 69. v pem (versions a/b/c/d) vs. temperature 0.801 0.8 0.799 0.798 0.797 0.796 0.795 ?40 120 100 80 ?20 0 20 60 40 t j , junction temperature ( c) 0.6705 v pem (versions e/f) (v) figure 70. v pem (versions e/f) vs. temperature 0.67 0.6695 0.669 0.6685 0.668 0.6675 0.667 0.6665 0.666 0.6655 2.905 ?40 120 100 80 ?20 0 20 60 40 k scale(max) t j , junction temperature ( c) figure 71. k scale(max) vs. temperature 2.9 2.895 2.89 2.885 2.88 2.875 2.87 2.865 2.86 2.855 40.1 40 39.9 39.8 39.7 39.6 39.5 39.4 39.3
ncp1341 www. onsemi.com 40 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp1341 www. onsemi.com 41 package dimensions soic?9 nb case 751bp issue a seating plane 1 5 6 10 h x 45 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.10mm total in excess of ?b? at maximum material condition. 4. dimensions d and e do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15mm per side. dimensions d and e are de- termined at datum f. 5. dimensions a and b are to be determ- ined at datum f. 6. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. d e h a1 a dim d min max 4.80 5.00 millimeters e 3.80 4.00 a 1.25 1.75 b 0.31 0.51 e 1.00 bsc a1 0.10 0.25 a3 0.17 0.25 l 0.40 1.27 m 0 8 h 5.80 6.20 c m 0.25 m dimension: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.37 ref l2 0.25 bsc a c 0.20 4 tips top view c 0.20 5 tips a-b d c 0.10 a-b 2x c 0.10 a-b 2x e c 0.10 b 9x b c c 0.10 9x side view end view detail a 6.50 9x 1.18 9x 0.58 1.00 pitch recommended 1 l f seating plane c l2 a3 detail a d on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1341/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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